Content addressable matrix memory cell and manufacture thereof

ABSTRACT

A CAM memory cellintegrated on a semiconductor substrateincludes a plurality of floating gate memory cells, matrix-organized in rows, called word lines, and columns, called bit lines. The cells belonging to a same row and have floating gate electrodes are short-circuited with each other in order to form a single floating gate electrodefor the CAM memory cell. Advantageously, the single floating gate electrodeis equipped with at least a cavity manufactured in at least a side wall of the single floating gate electrode. A process for manufacturing CAM memory cellsintegrated on a semiconductor substrateis also described.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a CAM (Content Addressable Matrix)memory cell and corresponding manufacturing process.

More specifically, the invention relates to a CAM memory cell integratedon a semiconductor substrate of the type comprising a plurality offloating gate memory cells, matrix-organized in rows, called word lines,and columns, called bit lines, said cells belonging to a same row andhaving floating gate electrodes being short-circuited with each other inorder to form a single floating gate electrode for said memory cell ofthe CAM type.

The invention also relates to a process for manufacturing memory cellsof the CAM type integrated on a semiconductor substrate.

The invention particularly relates, but not exclusively, to a CAM(Content Addressable Matrix) memory cell integrated on a semiconductorsubstrate and having a single floating gate electrode and the followingdescription is made with reference to this field of application forconvenience of illustration only.

2. Description of the Related Art

As it is well known, EPROM or FLASH-EPROM electronic memory devicesintegrated on a semiconductor substrate comprise a plurality ofmatrix-organized non-volatile memory cells; i.e., the cells areorganized in rows, called word lines, and columns, called bit lines.

With reference to FIG. 1, a vertical section along a word line is shown,of a plurality of non-volatile memory cells 1 integrated on asemiconductor substrate 2.

In particular, each single non-volatile memory cell 1 is manufactured incorrespondence with a respective active area 1 b which is insulated froman adjacent cell along a same word line by means of a thick oxide layer3. Each single cell 1 comprises a MOS transistor wherein the gateelectrode 4, located above a channel region and insulated therefrom bymeans of a thin oxide layer 5, is floating, i.e., it has a high DCimpedance towards all the other terminals of the same cell and of thecircuit wherein the cell is inserted.

The cell 1 also comprises a second electrode 6, called control gate,which is coupled to the floating gate electrode 4 and insulatedtherefrom by means of an interpoly oxide layer 7. The control gateterminal 6, as it is known, is driven by convenient control voltages.The other electrodes of the MOS transistor comprised in the cell 1 arethe usual drain, source and body terminals.

It is also known that EPROM or FLASH-EPROM electronic memory devices cancomprise memory cells of the CAM (Content Addressable Matrix) type,usually used to register configuration information and to use redundancyin electronic memory devices. In particular, CAM memory cells aremanufactured by using a plurality of traditional memory cells and theyhave a common floating gate terminal hanging over a plurality of channelregions of these traditional cells.

CAM memory cells are generally gathered in a sub-matrix spaced from thememory matrix. In particular, also CAM cells are organized in rows,called word lines, and columns, called bit lines.

A known configuration of a CAM memory cell is shown in FIG. 2,represented in vertical section, along a word line, and globallyindicated with 8.

In particular, the CAM memory cell 8 comprises five traditional memorycells whose floating gate electrodes are short-circuited with each otherto form a single floating gate electrode 9.

In order to increase the reading current of the CAM memory cell 8, it isknown to short-circuit four drain electrodes corresponding t thetraditional cells and to use them when reading the CAM memory cell 8 heremaining drain electrode is used for programming. In general, given Ntraditional cells comprised in the CAM memory cell 8, N-1 areshort-circuited with each other and used for reading operations, theremaining drain electrode being available for programming operations. heother body and source electrodes are common to all the cells belongingto the same CAM memory cell, similarly to what happens for the cells ofa traditional memory device.

With reference to FIGS. 3 to 6, the process for manufacturing a CAMmemory cell 8 is now described, as shown in the sectional view of FIG. 2taken along the line I-I of FIG. 6.

In particular, FIG. 3 illustrates a thick oxide layer 3 a formed on asemiconductor substrate 2 a that define active areas 3 b of the memorycell 8 (FIG. 2), according to the prior art.

Next, referring back to FIG. 2, a thin gate oxide layer 5 a o is grown,and a first polysilicon layer, called POLY 1, is then deposited anddoped.

Through a traditional photolithographic technique the first polysiliconlayer POLY 1 is etched to define a first size C, along word lines, ofthe single floating gate electrode 9 of the CAM memory cell 8. Inparticular, a first photolithographic mask 9a is used, shown in FIG. 4.

A second size D of the single floating gate electrode 9 is then definedby using a second photolithographic mask 9 b, as shown in FIG. 5.

FIG. 6 shows instead an overlapping of the masks 9 a and 9 b being usedwherein the outlines of a plurality of single floating gate electrodes 9of CAM memory cells 8 are highlighted with thick strokes.

The prior art manufacturing process goes on by foreseeing, traditionallyafter defining the single floating gate electrodes 9, the growth of aninterpoly oxide layer 7 a, typically comprising a series ofoxide/nitride/oxide layers, called ONO, and the deposition and furtheretching of a second polysilicon layer to define a control gate electrode6 a of the CAM memory cell 8, as shown in FIG. 2.

The implants for manufacturing the source and drain electrodes of CAMcells 8 formed on the substrate 2 a are then manufactured. The memorydevice is then completed by means of convenient metallization layers.

Although advantageous under several aspects, this known solution hasseveral drawbacks.

In fact, as it can be noticed by comparing FIGS. 1 and 2, the ONO layer7 a area between polysilicon layers, POLY 1 and POLY 2, of the CAMmemory cell 8, being said area represented in FIG. 2 along a size andbeing the other size given by the length D of the single floating gateelectrode 9 is smaller than the corresponding area of the sum of the ONOlayers 7 of five traditional matrix cells due to the contributions ofthe thickness A and of the distance B between the electrodes 4 oftraditional memory cells 1.

Therefore, it results that the capacitance C_(PP,CAM) of the CAM memorycell 8 between the first and second polysilicon layers, which isproportional to the area of the ONO layer 7 a covering the floating gateelectrode 9, is lower than the capacitance C_(PP,5MatrixCells) betweenthe first and second polysilicon layer of five traditional memory cells1. The other capacitances seen by the floating gate electrodes, 4 and 9respectively, are instead identical in both cases.

The capacitive coupling α_(G) is defined as the ratio between thecapacitance C_(PP) between the first and second polysilicon layers andthe overall capacitance C_(TOT) of the cell (i.e.,α_(G)=C_(PP)/C_(TOT)). Given that the capacitive coupling α_(G) of thefive traditional memory cells is equal to the coupling of a singlememory cell, i.e.:C_(PP,5MatrixCells)/C_(TOT,5MatrixCells)=C_(PP,1MatrixCell)/C_(TOT,1MatrixCell),and the difference in areas between the ONO layer 7 a of the CAM memorycell 8 and the ONO layer 7 of a traditional cell 1, a capacitivecoupling between the control electrode 6 a and the single floating gateelectrode 9 of the CAM memory cell 8 is lower than a capacitive couplingbetween the control gate terminal 6 and the gate electrode 4 of thesingle traditional matrix cell 1, i.e.:α_(G,CAM)=C_(PP,CAM/CTOT,CAM)<α_(G,1MatrixCell)=C_(PP,1 MatrixCell)/C_(TOT, 1 MatrixCell).

The known configuration of the CAM memory cells 8 thus implies lessefficient performances, mainly a considerable extension of cancellationtimes with respect to a traditional cell 1.

BRIEF SUMMARY OF THE INVENTION

An embodiment of the present invention provides a CAM memory cell,having such structural and functional features as to provide acapacitive coupling α_(G) similar to a traditional memory cell, thusovercoming the limits and drawbacks still affecting prior art memorydevices.

On embodiment of the present invention manufactures a CAM memory cellhaving a single floating electrode, obtained by short-circuitingfloating gate electrodes of traditional memory cells being adjacent witheach other and belonging to a same word line, wherein the singlefloating gate electrode is equipped with cavities.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The features and advantages of the CAM memory cell according to theinvention will be apparent from the following description of anembodiment thereof given by way of non-limiting example with referenceto the attached drawings.

In these drawings:

FIG. 1 is a sectional view of a portion of a memory device comprisingtraditional memory cells, according to the prior art;

FIG. 2 is a sectional view of a portion of a memory device comprising atraditional CAM memory cell, according to the prior art;

FIGS. 3 to 6 show some steps of a process for manufacturing traditionalCAM memory cells, according to the prior art;

FIGS. 7 to 10 show some steps of a first embodiment of a process formanufacturing CAM memory cells, according to the invention;

FIGS. 11 to 12 show some steps of a second embodiment of a process formanufacturing CAM memory cells, according to the invention;

FIG. 13 shows a CAM memory cell, according to one embodiment of theinvention; and

FIG. 14 is a perspective view of a portion of a floating gate electrodeof a CAM memory cell, according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

With reference to the FIGS. 7-14, a CAM (Content Addressable Matrix)memory cell and a corresponding manufacturing process are described.

The process steps described hereafter do not form a complete processflow for manufacturing integrated circuits. The present invention can beimplemented together with the integrated circuit manufacturingtechniques presently used in this field and only those commonly usedprocess steps which are necessary to understand the invention areincluded in the description.

The figures representing cross sections of integrated circuit portionsduring the manufacturing are not drawn to scale, but they are drawninstead in order to show the important features of the invention.

As mentioned with reference to the prior art, CAM memory cells arematrix-organized inside a memory device; i.e., these cells are organizedin rows, called word lines, and columns, called bit lines.

In particular, with reference to FIG. 13, a CAM memory cell 10manufactured according to the invention and integrated on asemiconductor substrate 11 is now described, which comprises a pluralityof traditional memory cells 12.

In the example of FIG. 13, the CAM memory cell 10 comprises fivetraditional memory cells 12, belonging to the same word line and eachone is manufactured in a respective active area 13 delimited by a thickinsulating layer 14. Each traditional memory cell 12 comprises a MOStransistor having a floating gate electrode insulated from thesemiconductor substrate 11 by means of a thin insulating layer 15 andrespective source and drain electrodes manufactured in the semiconductorsubstrate 11. The five floating gate electrodes of the memory cells 12are also short-circuited with each other in order to form a singlefloating gate electrode 16 of the CAM memory cell 10.

Typically, four drain electrodes of the memory cells 12 areshort-circuited with each other and used to read the CAM memory cell 10,while the remaining drain electrode is used to program this CAM memorycell 10. Moreover, the body and source electrodes are common to all theCAM cells 10 belonging to the same matrix, similarly to what happens fortraditional memory cell devices.

According to one embodiment of the invention, the floating gateelectrode 16 has at least a cavity 17 on the side walls as shown in FIG.16. Advantageously, the floating gate electrode 16 has a plurality ofcavities 17 manufactured in correspondence with the thick insulatinglayer 14.

Being L the length of the floating gate electrode 16 and P the depth ofeach cavity 17, in the embodiment shown in FIGS. 10 and 14, the depth Pis substantially equal to half the length of the floating gate electrode16, i.e., P≈L/2.

In particular, as illustrated in FIG. 10, cavities 17 are manufacturedin an alternating sequence (also referred to as an asymmetricaldistribution) along the side walls of the floating gate electrode 16corresponding to sides of the CAM memory cells 10 wherein the source anddrain electrodes are manufactured. FIG. 8 illustrates a firstphotolithographic mask 16b with an asymmetric distribution of openings16c that correspond to the alternating sequence of cavities.

An interpoly insulating layer 18,for example an ONO layer, covers thefloating gate electrode 16 17. A second conductive layer 19 a, forexample a polysilicon layer called POLY 2, formed on the interpolyinsulating layer 18 manufactures the control gate electrode 19 of theCAM memory cell 10.

With respect to prior art CAM memory cells 8 (FIG. 2), area of theinterpoly insulating layer 18 of the CAM memory cell 10 is increased. Inparticular, the CAM memory cell 10 of the present invention may have anet area gain of up to 20-30% over the CAM memory cell 8 of the priorart, which increases the capacitive coupling of the CAM memory cell 10to values close to the traditional memory cell 1.

In an alternative embodiment of the CAM memory cell according to theinvention, cavities 17 are manufactured only in correspondence with theside of the cell 10 wherein the source electrode is manufactured or onlyin correspondence with the side of the cell 10 wherein the drainelectrode is manufactured.

Actually, this embodiment requires a much higher precision in maskalignment since, even for small misalignments, an unacceptable leakageof the capacitive coupling values occurs.

According to a further alternative embodiment, as shown in FIG. 12,cavities 17 are symmetrically manufactured on two side walls of thefloating gate electrode 16 and they have a depth P1. That is, bothcavities of a pair of cavities are located directly opposite each otherin the side walls of the floating gate electrode 16. FIG. 1 1illustrates another first photolithographic mask 16 b with a symmetricdistribution of openings. 16 c that correspond to the symmetricaldistribution of notches on the two side walls of the floating gateelectrode 16.

In particular, the presence of symmetrical cavities with depth P1 in thefloating gate electrodes 16 allows the effect of a possible maskmisalignment for values lower than P1 to be partially nullified.

The possibility to nullify partially the effect of a possible maskmisalignment is also convenient for the manufacturing with cavitiesalternatively located as shown in FIGS. 8 and 10, when saidmanufacturing has the same number of cavities 17 on both sides of thefloating gate electrode 16.

Clearly, the distance S between two symmetrical cavities must be equalto the minimum length on the floating gate electrode 16, and it must besufficiently lower than the length L of this electrode in order to allowdeposition in the cavities 17 of the conductive layer 19 a and in themeantime sufficiently thick to resist to etching after the definition ofthe control gate electrode 19.

With reference to FIGS. 7 to 13, the manufacturing process of a CAMmemory cell 10 according to the invention is now described.

In particular, a thick insulating layer 14, for example oxide, is formedon a semiconductor substrate 11 in order to define active areas 13 offloating gate memory cells 12.

Afterwards, a thin gate insulating layer 15, for example oxide, is grownand a first conductive layer 16a, for example a polysilicon layer calledPOLY 1, is then formed.

As shown in FIG. 8, by means of a traditional photolithographictechnique using a first photolithographic mask 16 b, the firstconductive layer 16 a is etched to define a first size E, along the wordlines, of a single floating gate electrode 16 of the CAM memory cell 10.

According to one embodiment of the invention, the firstphotolithographic mask 16 b is equipped with a plurality of openings 16c which are partially aligned with portions of the first conductivelayer 16 a which will manufacture the single final floating gateelectrode 16. Therefore, during the etching step of the first conductivelayer 16 a, those portions of the first conductive layer 16 a beingexposed from openings 16 c are also removed.

Advantageously, these openings 16 c are manufactured in correspondencewith the thick insulating layer 14.

The second size L of the single floating gate electrode 16 is thendefined through a traditional photolithographic technique which uses asecond photolithographic mask 16 d, shown in FIG. 9.

After a second etching step of the first conductive layer 16 a by meansof the second photolithographic mask 16 d, the single floating gateelectrode 16 is then formed, equipped with cavities 17 on the side wallsobtained by removing the first conductive layer 16 a in correspondencewith openings 16 c.

FIG. 10 shows an overlapping of the masks used in the process accordingto the invention wherein the outlines of the floating gate electrodes 16of CAM memory cells 10 according to one embodiment of the invention havebeen highlighted with thick strokes.

According to one embodiment of the invention, by varying the arrangementof openings 16 c, different positions and depths of cavities 17 can bedefined in the side walls of the floating gate electrode 16. Forexample, FIG. 11 shows an alternative embodiment of the firstphotolithographic mask 16 b having a symmetric distribution of openings16 c for defining a symmetric distribution of cavities in the singlefloating gate electrode 16 as illustrated in FIG. 12.

Referring to FIG. 13, and according to the invention, finalmanufacturing process steps include formation of an interpoly insulatinglayer 18 on the floating gate electrode 16. The interpoly insulatinglayer 18 is for example an oxide layer typically comprising a series ofoxide/nitride/oxide layers, called ONO. A control gate electrode 19 isthen defined, manufactured by means of a second conductive layer 19 a.

The implants for manufacturing the source and drain electrodes of CAMcells 10 are then manufactured. The memory device is then completed bymeans of convenient metallization levels.

In conclusion, CAM memory cells according to some embodiments of theinvention allow reduced cancellation times and generally more efficientperformances to be obtained, in line with traditional matrix cells. Thisis done through an alternative drawing of the floating gate electrode 16of CAM memory cells 10 by changing only one mask during the definitionprocess of the latter, thus without increasing the number thereof and inorder to manufacture cavities 17 in this floating gate electrode 16.

All of the above U.S. patents, U.S. patent application publications,U.S. patent applications, foreign patents, foreign patent applicationsand non-patent publications referred to in this specification and/orlisted in the Application Data Sheet are incorporated herein byreference, in their entirety.

From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

1. A CAM memory cell integrated on a semiconductor substrate,comprising: a plurality of floating gate memory cells, matrix-organizedin rows, called word lines, and columns, called bit lines, saidcellsbelonging to a same row and having floating gate electrodes being witheach other in order to form a single floating gate electrode for saidCAM memory cell, the single floating gate electrode is equipped with acavity manufactured in a side wall of said single floating gateelectrode.
 2. A CAM memory cell according to claim 1, wherein the singlefloating gate electrode comprises a plurality of cavities.
 3. A CAMmemory cell according to claim 2, wherein said cavities are manufacturedin an alternating sequence in a first and a second side wall of saidsingle floating gate electrode.
 4. A CAM memory cell according to claim2, wherein said cavities are provided on two side walls of said singlefloating gate electrode.
 5. A CAM memory cell according to claim 4,wherein said cavities are symmetrically located on said side walls ofsaid single floating gate electrode.
 6. A CAM memory cell according toclaim 1, wherein said floating gate memory cells are manufactured inrespective active areas delimited by a thick insulating layer, whereinsaid cavity is manufactured in correspondence with said thick insulatinglayer.
 7. A CAM memory cell acc claim 1, wherein said plurality offloating gate memory cells comprises five floating gate memory cells. 8.A process for manufacturing CAM memory cells integrated on asemiconductor substrate that includes a plurality of floating gatememory cells, matrix-organized in rows, called word lines, and columns,called bit lines, said cells belonging to a same row and having floatinggate electrodes being short-circuited with each other in order to form asingle floating gate electrode for said CAM memory cells, the processcomprising the following steps: manufacturing in said semiconductorsubstrate a plurality of active areas insulated from each other by meansof a thick insulating layer; cascade-forming a thin insulating layer anda first conductive layer on said semiconductor substrate; forming saidsingle floating gate electrode in said first conductive layer, saidsingle floating gate electrode being continuous on a plurality of activeareas belonging to a same matrix row forming a cavity on a side wall ofsaid single floating gate electrode.
 9. A process for manufacturing CAMmemory cells according to claim 8, wherein said steps of forming saidsingle floating gate electrode and said cavity comprise the followingsteps: using a first photolithographic mask to define in said firstconductive layer a first size along said matrix row of said single gateelectrode and an opening delimiting said cavity in said single floatinggate electrode; using a second photolithographic mask to define in saidfirst conductive layer a second size of said single floating gateelectrode along a matrix column.
 10. A process for manufacturing CAMmemory cells according to claim 9, wherein said opening is aligned withsaid thick insulating layer.
 11. A process for manufacturing CAM memorycells according to claim 9, comprising forming a plurality of cavitiesin said side wall of said single floating gate electrode.
 12. A processfor manufacturing CAM memory cells according to claim 11, wherein saidfirst mask comprises a plurality of openings.
 13. A process formanufacturing CAM memory cells according to claim 12, wherein saidopenings are located alternatively with respect to side walls of saidsingle floating gate electrode.
 14. A process for manufacturing CAMmemory cells according to claim 12, wherein said openings are locatedsymmetrically with respect to side walls of said single floating gateelectrode.
 15. A process for manufacturing CAM memory cells according toclaim 8, further comprising the steps of: forming an interpolyinsulating layer to cover said single floating gate electrode and coversaid at least one cavity; and forming a second conductive layer on saidinterpoly insulating layer to define a second control electrode.
 16. ACAM memory cell integrated on a semiconductor substrate, comprising: aplurality of memory cells; a floating gate electrode coupled to theplurality of memory cells, the floating gate electrode having a firstside wall and a second side wall; and a plurality of cavities formed inthe first side wall and the second side wall.
 17. The CAM memory cell ofclaim 16, wherein the plurality of cavities are formed in an alternatingsequence in the first and second side walls.
 18. The CAM memory cell ofclaim 16, wherein a first plurality of cavities formed in the first sidewall are directly aligned with a second plurality of cavities formed inthe second side wall.
 19. The CAM memory cell of claim 16, wherein eachmemory cell of the plurality of memory cells comprises ametal-oxide-silicon transistor, the MOS transistor having an active areaelectrically isolated from other memory cells of the plurality of memorycells by thick insulating layers.
 20. The CAM memory cell of claim 19,wherein the plurality of cavities are aligned with the thick insulatinglayers.
 21. The CAM memory cell of claim 19, further comprising: acontrol gate electrode; and an insulating layer formed between thecontrol gate electrode and the floating gate electrode.
 22. The CAMmemory cell of claim 21, wherein the insulating layer is an interpolyinsulating layer.
 23. The CAM memory cell of claim 16, wherein thefloating gate electrode is a contiguous electrode.
 24. A memory deviceintegrated on a semiconductor substrate, comprising: a plurality of CAMmemory cells each including: a plurality of floating gate memory cells;a floating gate electrode coupled to the plurality of memory cells, thefloating gate electrode having a side wall; and a plurality of cavitiesformed in the side wall.